EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...
Semiconductor Engineering

The History Of CMOS

Since CMOS has been around for about 50 years, a comprehensive history would be a book. This blog focuses on what I consider the major transitions. Before CMOS, there was NMOS (also PMOS, but I have ...
Electronics Weekly

Imec makes CMOS GAA nanowire mosfets

Imec has achieved the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs. Key in the integration scheme is a dual-work-function metal gate enabling matched threshold ...
Design-Reuse

BCD Technology: A Unified Approach to Analog, Digital, and Power Design

Since its inception, BCD technology has leveraged the integration of two primary technologies—polysilicon gate CMOS and DMOS power architecture—on the same chip. Its compatibility with bipolar ...
Semiconductor Engineering

IBM, Intel And TSMC Roll Out finFETs

At the IEEE International Electron Devices Meeting (IEDM) in San Franciso, IBM, Intel and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) this week will separately present the latest details of ...