EDN

16MB Radiation-Hardened SRAM

The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user ...
Electronic Design

High-Density, Low-Power 32M CMOS SRAM

Alliance Memory today expands its line of legacy low-power CMOS SRAMs with a new 32M IC (2M x 16 / 4M x 8 switchable), the company's highest density low-power device to date. A line of legacy ...
Electronic Design

Crolles2 Alliance reveals ultra-dense SRAM cell in 45 nm conventional bulk CMOS

The Crolles2 Alliance, which includes Freescale Semiconductor, Philips and STMicroelectronics, has created six-transistor SRAM-bit cells with an area of less than 0.25 square microns, or about half ...
EDN

ST-coordinated Pullnano consortium pushes ahead with 32-, 22-nm CMOS

The Brussels-based European Commission-sponsored, and STMicroelectronics-managed project Pullnano is reporting the creation of a functional CMOS SRAM demonstrator built using 32-nm design rules, along ...