Business Insider

Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs

SAN JOSE, Calif., April 20, 2021 /PRNewswire/ -- Movellus, Inc. today announced its Maestro™ Intelligent Clock Network platform that intelligently orchestrates clock distribution in SoC designs. The ...
Ars Technica

Is SOC clock speed still the primary determinant of phone performance?

You can pick a stormingly high clocked SoC with a low end architecture (e.g. A53, A55) and eMMC storage, or one with high end architecture (A72, 73, 75) and UFS storage with moderate to quite low ...
Semiconductor Engineering

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design

A new technical paper titled “A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems” was published by researchers at Hongik University, Seoul, South Korea. “An all-digital ...
EDN

Video encoding, SoC development, and TI’s DSP architecture

Video encoding is one of the most challenging problems faced by current video SoC designers due to very high computation complexity and data bandwidth requirements. This challenge gets compounded by a ...
EDN

Networking-SOC case study: Conservative architecture, aggressive process

As the performance benefits of new CMOS process geometries become more and more tenuous (see, for instance, “TSMC talks details on the meaning of 45-nm CMOS“), designers are finding that system ...
Semiconductor Engineering

Clocks Getting Skewed Up

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it’s fraught with the most problems at the ...
Electronic Design

SiTime Launches Cascade family of MEMS Clock ICs for Demanding Embedded Apps

SiTime unveiled the Cascade family of MEMS clock ICs for 5G, wireline telecom, and datacenter infrastructure applications. This clock-system-on-a-chip family, the SiT9514x, consists of clock ...