Electronic Design

Imec Teams With Cadence on DFT Solution for 3-D Memory-on-Logic

January 25, 2013. At the European 3D TSV Summit in Grenoble, France, on January 22-23, 2013, imec announced that together with Cadence Design Systems they have developed, implemented, and validated an ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

IC vendors detail enhanced DFT methods

CHARLOTTE, N.C. — Engineers from three semiconductor companies detailed their experience using novel design-for-test techniques to speed chip testing during volume manufacturing at the International ...
Semiconductor Engineering

Test Hyperconvergence In Semiconductor Development

Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The development team threw the chip “over the wall” to the test engineers, who ...