Have you ever wondered how a predator succeeds or its prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) as it chases prey (say, a deer). The VLSI ...

Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...

Statistical static timing analysis (SSTA)—theory, thesis project, IBM proprietary technology—is about to add one more stage to its evolution: mainstream member of the design flow. For some time now ...

Ever-growing chip size and complexity put pressure on every step and every electronic design automation (EDA) tool in the development flow. More decisions must be made at the architectural stage, ...

In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot ...

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...