EDN

Cadence TimingVision supports high-speed PCB interface design

Cadence has announced a new TimingVision technology within the Allegro PCB Designer solution that can speed the timing closure of high-speed PCB interfaces — such as a DDR3 memory interface — by 60% ...
Design-Reuse

Rambus Introduces High-Performance DDR3 Memory Controller Interface Solution for Consumer Electronics

LOS ALTOS, Calif., Jul 28, 2010 -- Rambus Inc. (NASDAQ:RMBS), one of the world's premier technology licensing companies, today announced a high-performance, low-cost DDR3 memory controller interface ...
EDN

Designing DDR3 SDRAM controllers with today’s FPGAs

The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet ...
Design-Reuse

Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2

The emerging DDR3 memory standard will extend the performance range of DDR memories considerably, while maintaining some amount of backwards compatibility with the existing DDR2 memory standard. It is ...