EDN

‘Smart’ verification moves beyond SystemVerilog 3.0

HDL simulation tools need to evolve to become a verification platform by making “smart verification” technologies, such as testbench features, assertion technologies, advanced coverage technologies, ...
EDN

SystemVerilog reference verification methodology: RTL

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Design-Reuse

ARM And Synopsys to Deliver Industry’s First Reference Verification Methodology Based on SystemVerilog

Companies to Publish “SystemVerilog Verification Methodology Manual,†a “How-To†Book on Verification Using SystemVerilog CAMBRIDGE, UK AND MOUNTAIN VIEW, Calif. – February 16, 2004 - ARM ...
New Electronics

Imperas and Synopsys collaborate on SystemVerilog based RISC-V verification

Imperas Software, a specialist in RISC-V models and simulation solutions, is working with Synopsys to address the growing demand for RISC-V processor verification. This collaboration is intended to ...