Programming Zynq SoCs with MATLAB and Simulink - MathWorks
Learn to develop and configure models in Simulink and deploy on Xilinx Zynq-7000 SoCs for software/hardware codesign in this instructor-led course.
FPGA Design and Codesign - AMD System Generator and HDL Coder
Modeling and Simulation Simulink for Model-Based Design enables you to reduce development time for AMD FPGA and Zynq SoC applications by modeling the hardware implementation at a high-level …
Zynq UltraScale+ RFSoC Design with MATLAB and Simulink
Characterize, prototype, deploy, and verify multichannel wireless systems on AMD Zynq UltraScale+ RFSoC with MATLAB and Simulink.
Generate IP Core with AXI-Stream Interface - MathWorks
Use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware.
AMD SoC Support from SoC Blockset - Hardware Support - MathWorks
SoC Blockset Support Package for AMD FPGA and SoC Devices enables you to design, evaluate, and implement SoC hardware and software architectures on AMD FPGAs and AMD Zynq ® SoCs and …
Get Started with IP Core Generation from Simulink Model
3 days ago · This example shows how to use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® ZC702 evaluation kit.
Getting Started with VxWorks 7 on AMD Zynq Boards
This example shows how to generate and run code from a Simulink® model onto an AMD Zynq® ZC702 evaluation kit with a VxWorks® 7 operating system.
Programming Zynq RFSoCs Using Simulink - MathWorks
Develop and configure models in Simulink and deploy on Xilinx Zynq UltraScale+ RFSoCs.
Generate IP Core with AXI4-Lite Interface - MATLAB & Simulink
Introduction This example is a step-by-step guide that helps you use the HDL Coder™ software to generate a custom HDL IP core which blinks LEDs on the Xilinx Zynq UltraScale+ MPSoC ZCU102 …
Generate IP Core with AXI4-Stream Video Interface
This example shows how to use the AXI4-Stream Video interface to enable high speed video streaming on the generated HDL IP core.